Random access memory (RAM) is a type of storage for computing devices. RAM is typically associated with volatile memory that is implemented in integrated circuits and in which stored information is lost when power provided to the RAM is switched off.
One type of RAM is known as DDR SDRAM (double-data-rate synchronous dynamic random access memory). DDR SDRAM is typically used in computing applications that require high bandwidth and low latency memory access. One version of this memory technology is known as DDR3 SDRAM, which can provide for high performance data rates, high bandwidth, high density, and low power consumption relative to earlier generations of SDRAM.
The high bandwidth and high operating frequencies required to drive DDR SDRAM can be problematic as they can make the controller to memory interface electrically complex due to signal integrity considerations. A DDR3 SDRAM controller and associated memory may perform read and write operations synchronously based on a periodic signal transmitted over a “strobe” line. Static and dynamic timing variations between the strobe line and a data line can cause memory errors. Static variations that cause timing skew between the strobe and data lines may be due to, for example, on-die process and wire variations across strobe and data logic, on-chip power supply grid variations, package and board interconnect, and material variations. Dynamic timing variations may be caused by short or long term voltage drift and temperature changes during functional operation of the interface
The strobe line may be used to signal the beginning and end of burst of data being written to or read from the DDR3 SDRAM. A “preamble cycle” may be used to indicate the beginning of a write or read burst of a data transfer between controller and memory. A “postamble cycle” may be used to signal the end of a write or read burst of a data transfer between controller and memory. For high frequency memory operation, generation of the write preamble and postamble cycles are not trivial as the cycles should be initiated without causing glitches or false edges from propagating to the memory, which could potentially cause incorrect interpretation of a value being written.